This application is the national phase under 35 U.S.C. xc2xa7 371 of PCT International Application No. PCT/KR02/01255 which has an International filing date of Jul. 3, 2002, which designated the United States of America, which claims priority based on Korean Application No. 01-40155 filed Jul. 5, 2001.
The present invention relates to method of modulating a series of data words into (d,k) constrained sequence with good suppression of a direct current (DC) component.
When data is transmitted through a transmission line or recorded onto a recording medium such as a magnetic disk, an optical disk or a magneto-optical disk, the data is modulated into code matching the transmission line or the recording medium prior to the transmission or recording.
Run length limited codes, generically designated as (d,k) codes, have been widely and successfully applied in modern magnetic and optical recording systems. Such codes, and means for implementing said codes, are described by K. A. Schouhamer Immink in the book entitled xe2x80x9cCodes for Mass Data Storage Systemsxe2x80x9d (ISBN 90-74249-23-X, 1999).
Run length limited codes are extensions of earlier non return to zero recording (NRZ) codes, where binarily recorded xe2x80x9czerosxe2x80x9d are represented by no (magnetic flux) change in the recording medium, while binary xe2x80x9conesxe2x80x9d are represented by transitions from one direction of recorded flux to the opposite direction.
In a (d,k) code, the above recording rules are maintained with the additional constraints that at least d xe2x80x9czerosxe2x80x9d are recorded between successive data xe2x80x9conesxe2x80x9d, and no more than k xe2x80x9czerosxe2x80x9d are recorded between successive data xe2x80x9conesxe2x80x9d. The first constraint arises to obviate intersymbol interference occurring due to pulse crowding of the reproduced transitions when a series of xe2x80x9conesxe2x80x9d are contiguously recorded. The second constraint arises in recovering a clock from the reproduced data by xe2x80x9clockingxe2x80x9d a phase locked loop to the reproduced transitions. If there is too long an unbroken string of contiguous xe2x80x9czerosxe2x80x9d with no interspersed xe2x80x9conesxe2x80x9d, the clock regenerating phase-locked-loop will fall out of synchronism.
In, for example, a (2,7) code there is at least two xe2x80x9czerosxe2x80x9d between recorded xe2x80x9conesxe2x80x9d, and there are no more than seven recorded contiguous xe2x80x9czerosxe2x80x9d between recorded xe2x80x9conesxe2x80x9d. The series of encoded bits is converted, via a modulo-2 integration operation, to a corresponding modulated signal formed by bit cells having a high or low signal value, a xe2x80x98onexe2x80x99 bit being represented in the modulated signal by a change from a high to a low signal value or vice versa. A xe2x80x98zeroxe2x80x99 bit is represented by the lack of change of the modulated signal.
As described above, when data is transmitted through a transmission line or recorded onto a medium, the data is modulated into a coded sequence matching the transmission line or recording medium prior to the transmission or recording. If the coded sequence resulting from the modulation contains a direct current (DC) component, a variety of error signals such as tracking errors generated in control of a servo of the disk drive become prone to variations or jitter are generated easily.
The first reason for using said dc-free signals is that recording channels are not normally responsive to low-frequency components. The suppression of low-frequency components in the signal is also highly advantageous when the signal is read from an optical record carrier on which the signal is recorded in the track, because then continuous tracking control undisturbed by the recorded signal is possible.
A good suppression of the low-frequency components leads to improved tracking with less disturbing audible noise. For this reason it is thus desirable to make as many efforts to prevent the modulated sequence from containing a direct current component as possible.
In order to prevent the modulated sequence from containing a direct current component, control of a DSV (Digital Sum Value) to prevent the modulated signal from containing a direct current component has been proposed. The DSV is a total found by adding up the values of a train of bits, wherein the values +1 and xe2x88x921 are assigned to xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 in the train respectively, which results after NRZI modulation of a train of channel bits. The DSV is an indicator of a direct current component contained in a train of sequences.
A substantially constant running digital sum value (DSV) means that the frequency spectrum of the signal does not comprise frequency components in the low frequency area. Note that DSV control is normally not applied to a sequence generated by a standard (d,k) code. DSV control for such standard (d,k) codes is accomplished by calculating a DSV of a train of encoded bits after the modulation for a predetermined period of time and inserting a predetermined number of DSV control bits into the train of encoded bits. In order to improve the code efficiency it is desirable to reduce the number of DSV control bits to a smallest possible value.
An example of the use of modulated signals to record and read an audio signal on an optical or magneto-optical record carrier can be found in U.S. Pat. No. 4,501,000. The specification describes the Eight-to-Fourteen (EFM) modulation system, which is used for recording information on Compact Disks (CD) or MiniDisk (MD). The EFM-modulated signal is obtained by converting a series of 8-bit information words into a series of 14-bit code words, and where 3-bit merging words are inserted between consecutive code words.
Respective code words of 14 bits satisfy the conditions that at least d=2 and at most k=10 xe2x80x9c0xe2x80x9ds are placed between two xe2x80x9c1xe2x80x9ds. In order to satisfy this condition also between code words, 3-bit merging words are used. Four 3-bit merging words of 8 possible 3-bit merging words are permitted to be used, namely xe2x80x9c001xe2x80x9d, xe2x80x9c010xe2x80x9d, xe2x80x9c000xe2x80x9d, and xe2x80x9c100xe2x80x9d. The remaining possible 3-bit merging words, namely xe2x80x9c111xe2x80x9d, xe2x80x9c011xe2x80x9d, xe2x80x9c101xe2x80x9d, and xe2x80x9c110xe2x80x9d are not used as they violate the prescribed d=2 constraint.
One of the four allowed merging words is selected such that the bit string obtained after cascading alternate code words and merging words satisfies the (d,k)-constraint, and that in the corresponding modulo-2 integrated signal the DSV remains substantially constant. By deciding the merging words according to above rules, low-frequency components of the modulated signal can be reduced.
In the meantime, information recording still has a constant need for increasing the reading and writing speed. The aim of increased reading speed, however, requires higher servo bandwidth of the tracking mechanism, which, in turn, sets more severe restrictions on the suppression of the low-frequency components in the recorded signal.
Improved suppression of the low-frequency components is also advantageous for suppressing audible noise arising from the tracking mechanism. For this reason, it is desirable to make as many efforts to prevent the signal from containing low-frequency components.
It is an object of the present invention to provide a coding system which is able to generate for each data word a corresponding sequence, which can suppress dc-components precisely, and does not contain long string of xe2x80x980xe2x80x99s, and long runs of the smallest runlength d, under the rules of the (d,k) code for recording onto a recordable medium.
A method of converting a series of data word into a modulated signal according to the present invention generates for each data word a number of alternative sequences by combining mutually different digital words with the data word, translates each alternative sequence into a (d,k) constrained sequence according to a predefined coding rate m/n, detects development of digital sum every bit for each translated (d,k) constrained sequence and checks whether or not each development of digital sum is beyond a preset threshold, sorts out the translated (d,k) constrained sequences based on whether each development of digital sum is ever beyond the preset threshold, and selects one (d,k) constrained sequence, of which development of digital sum has the least maximum value, among the sorted-out sequences for recording onto a recordable medium or transmission through channel.
The above-characterized method of converting a series of data words into a modulated signal according to the present invention, makes it possible to suppress DC component of sequences precisely for recording onto a recordable medium such as an optical disk or a magneto-optical disk, while excluding sequences with a sync pattern, long string of xe2x80x980xe2x80x99s, and long runs of the smallest runlength d under the rules of the (d,k) code.
This invention can suppress DC component more remarkably in case that a sequence becomes longer.